The present invention relates to a method of making a dynamic random access memory and more particularly to a method of making a dynamic random access memory with dual cell plate structure.
Conventionally, a dynamic random access memory (DRAM) cell has a capacitor and a metal oxide semiconductor(MOS) transistor.
The capacitor has a plate node, a storage node and a dielectric film. The MOS transistor has a source electrode, a drain electrode and a gate electrode.
In the above mentioned DRAM cell, since the DRAM cell only has a capacitor and a MOS transistor, it is possible to considerably reduce the cost in manufacturing the DRAM cell for each bit and to advantageously store a large quantity of information.
Therefore, DRAM has been widely used as not only the main storage memory of large-sized computers but also the memory element of personal computers. Presently, the capacitor is the key in designing a DRAM cell. So as to store information, the capacitor should be designed such that the capacitor has a capacitance as large as possible.
Also, so as to have a large capacitance, the capacitor should be designed such that it has an area as wide as possible and a dielectric film as thin as possible.
Further, the capacitor should be designed such that the capacitor has a junction capacitance with a storage electrode as high as possible and a junction capacitance with a bit line as low as possible.
Referring to FIGS. 1a, 1b and FIGS. 2a to 2f, there is illustrated a method of making a conventional DRAM with a dual capacitor-plate cell (hereinafter, DCP structure) which satisfies the above-conditions.
First, FIG. 1a shows a plane view of a one bit DRAM cell having a DCP cell structure.
FIG. 1b shows a cross sectional view taken along a line A--A' of FIG. 1a.
A method of making a conventional DRAM with a DCP cell structure shown in FIG. 1a, 1b will be hereinafter described, in conjunction with FIGS. 2a to 2f.
Referring to FIGS. 2a to 2f, there are shown key process steps of making the conventional DRAM shown in FIGS. 1a and 1b.
As shown in FIG. 2a, first, capacitor buried contacts are opened after the formation of a bit line 1. A polysilicon buffer layer 2 is then delineated.
As show in FIG. 2b, chemical vapour deposition (CVD) oxide 3 is deposited and the surface becomes plane by the oxide etch back technique.
Then, the triple layer of lower cell plate 4 of 200 nm thick polysilicon, first thin dielectrics 5 of oxide-nitride-oxide film(teff=5 nm) and storage node 6 of 500 nm thick polysilicon are deposited successively. As shown in FIG. 2c, capacitor contact holes 7 are opened through these composite layers to the polysilicon buffer layer 2.
Subsequently, as shown in FIG. 2d, CVD oxide 8 having a thickness of 100 nm is deposited and etched by anisotropic etching to make the self aligned sidewall dielectrics 9 in the capacitor contact holes 7. These sidewall dielectrics 9 electrically isolate the storage node 6 and the lower cell plate 4.
Subsequently, thin polysilicon film 10 having a thickness of 100 nm thick is deposited to connect the polysilicon buffer layer 2 and the polysilicon storage node 6, as shown in FIG. 2e.
The storage node resist patterns are delineated and the polysilicon storage node 6 is etched by the reactive ion etch(RIE) technique to a desired pattern. This etching of polysilicon is stopped at the thin ONO film 5 as a result of the high selective etching of polysilicon in comparison to oxide.
The formation of a second ONO film 11 having an effective oxide thickness of 5 nm is performed.
As shown in FIG. 2f, the upper cell plate node 12 of polysilicon having a thickness of 300 nm thick is deposited.
At this time,the capacitor contact holes 7 and the isolation spaces between storage nodes are filled by this upper cell plate node 12.
Therefore, the surface of cell array becomes plane automatically.
According to FIG. 26, as mentioned above, the CVD oxide 3 is deposited and the contact holes 7 are opened.
Also, the first aluminum layer, that is, the bit line 1 stitches the polysilicon word line to reduce the word line resistance for improved speed performance.
One of the advantages of this process is that no extra mask process is necessary to fabricate this cell structure to the conventional stacked capacitor cell with the exception of the polysilicon buffer layer 2.
Another advantage is that the storage capacitors above can be delineated easily on the relatively flat surface for their patterning.
Also, it is possible to obtain capacitors having areas which are relatively wider than that of the conventional capacitors.
According to the conventional method, however, since the thicknesses of the word line and the insulation film (for example, CVD oxide) are self-aligned and hence limited automatically, there are disadvantages in that the parasitic capacitance between the word line and the bit line becomes large and the word line may be shorted to the bit line.